This router only has one ethernet port, so a VLAN is useless here, now that the rt3050 TCP bug that happened without VLANs has been fixed for a very long time.

Add this router to the VLAN-less config that is used by other single-port routers.

Also fix MAC address detection code since this router has no WAN port.

Signed-off-by: Vittorio Gambaletta <openwrt@vittgam.net>

Some routers only have one port, so eth0 is used without VLANs for them.

Revision r47720 introduced some changes, but wrongly confused "enable" with "reset".

VLANs need to be disabled for those routers, and the switch may be reset.

Fix this, by explicitly disabling VLANs instead of resetting the switch for these routers.

Also merge duplicate configuration for the "m2m".

Signed-off-by: Vittorio Gambaletta <openwrt@vittgam.net>

The new rt3050 switch driver doesn't have problems with TCP when not
using VLANs.

This piece of code also broke failsafe for all routers where the LAN
port is not wired to port 0 of the internal switch.

Signed-off-by: Vittorio Gambaletta <openwrt@vittgam.net>

SVN-Revision: 49293

Port 0 is the only ethernet port on this router, so disable all other PHYs
in order to save power.

Signed-off-by: Vittorio Gambaletta <openwrt@vittgam.net>

SVN-Revision: 49292

Port 4 is the only ethernet port on this router, so disable all other PHYs
in order to save power.

Signed-off-by: Vittorio Gambaletta <openwrt@vittgam.net>

SVN-Revision: 49291

This patch allows configuring ports to be disabled in the device tree; this
saves power, since disabling ports here actually disables power to ethernet
PHYs.

Line 444 enables all ethernet ports, so line 487 is getting zero ports to be
disabled, except for port 5 in SoCs where this is not implemented as it will
be sticky disabled in register POC0. Because of this, the code will still read
the switch configuration and OR it to the device tree setting.

Signed-off-by: Vittorio Gambaletta <openwrt@vittgam.net>

SVN-Revision: 49290

Line 444 is actually enabling all switch ports by setting the disable bits
to 0. This needs to be done because the bootloader sets all ports to disabled
by default (which is the case for at least one router based on RT5350).

So, this patch fixes the comment in line 443.

Signed-off-by: Vittorio Gambaletta <openwrt@vittgam.net>

SVN-Revision: 49289

The prefix used in the driver is now "mediatek" instead of "ralink".

Signed-off-by: Vittorio Gambaletta <openwrt@vittgam.net>

SVN-Revision: 49288

The FCT2 esw register should be set to 0x2500C to have "unknown IPv6
multicast" packets broadcasted to every port, instead of dropped.
The previous value only let those packets go through ports 1 and 3.

"Unknown IPv6 multicast" packets include packets needed by ICMPv6 echo
requests addressed to well-known addresses, such as ff02::1 (MAC address
is 33:33:00:00:00:01 in this case).

Please note that by default ICMPv6 echo requests to ff02::1 are not replied
to by the router because of ip6tables considering those packets to be invalid.
But this is another bug/patch. ;)

Signed-off-by: Vittorio Gambaletta <openwrt@vittgam.net>

SVN-Revision: 49287

This patch adds support for the TP-Link TL-WR810N.
https://wiki.openwrt.org/toh/tp-link/tl-wr810n



Signed-off-by: Jens Steinhauser <jens.steinhauser@gmail.com>

SVN-Revision: 49286

Currently system log is always included as a part of ubox.
Add logd as a seperate package and add it to default packages list.

Signed-off-by: Andrej Vlasic <andrej.vlasic@sartura.hr>

SVN-Revision: 49285

VGV7510KW2 with VRX288 v1.2 has brnboot 1.8 installed. Starting with
this brnboot version, the "GPHY Clock Source" isn't set anymore by
brnboot, with the result that xrx200-net fails to probe/initialize the
phys.

Use the phy clock source device tree binding to specify the clock source.

Signed-off-by: Mathias Kresin <openwrt@kresin.me>

SVN-Revision: 49284

Signed-off-by: Mathias Kresin <openwrt@kresin.me>

SVN-Revision: 49283

Signed-off-by: Mathias Kresin <openwrt@kresin.me>

SVN-Revision: 49282

brnboot based devices can have two Image partitions. When flashing
images via the brnboot recovery web interface, the Image partitions are
written alternating.

The current active Image partition is stored in the first byte of the
Primary_Setting partition by using 0x00 for Code_Image_0 and 0x01 for
Code_Image_1.

By using the information about the active "Code Image", it is possible
to ensure that the rootfs belongs to the current booted Image/Kernel.

Signed-off-by: Mathias Kresin <openwrt@kresin.me>

SVN-Revision: 49281

Starting with kernel 4.4, the use of partitions as direct subnodes of the
mtd device is discouraged and only supported for backward compatiblity
reasons.

Signed-off-by: Mathias Kresin <openwrt@kresin.me>

SVN-Revision: 49280

Use the same name for TP-Link images as it was with the old image build
code.

Move the BOARD_ID export to the TP-Link image build recipe, to indicate
that the variable is only related in this context.

Signed-off-by: Mathias Kresin <openwrt@kresin.me>

SVN-Revision: 49279

Based on the vg3503j_gphy_led.sh script published in the VG3503J wiki
article, the OEM Firmware uses the following PHY led functionality:

    gphy led 0: LINK/ACTIVITY
    gphy led 1: LINK
    gphy led 2: ACTIVITY

Signed-off-by: Mathias Kresin <openwrt@kresin.me>

SVN-Revision: 49278

Fix eth0 support for the Ubiquiti UniFi AP AC
Signed-off-by: Paul Wassi <p.wassi at gmx.at>

SVN-Revision: 49277

The VGV7510KW22 has the leds for LAN1-3 connected to pin1 of the phys
and the led for LAN4 connect to pin0 of the phy. This results with the
current configuration in a fast flashing LAN4 led as soon as a network
cable is connected. Something similar was reported on the forum[1] for
the VGV7519 as well.

Since it isn't predicable to which pin a (single) phy led is connected,
use the (default) pin1 functionality

    Constant On: 10/100/1000MBit
    Blink Fast: None
    Blink Slow: None
    Pulse: TX/RX

for all ethernet phy leds.

After checking pictures of all vr9 boards, it looks like only the VG3503J
has more than one led connected per phy. Using the phy led device tree
bindings to assign the functionality to the "additional" leds, the
VG3503J phy leds should behave as before.

Signed-off-by: Mathias Kresin <openwrt@kresin.me>

[1] https://forum.openwrt.org/viewtopic.php?pid=321523

SVN-Revision: 49270

Signed-off-by: Mathias Kresin <openwrt@kresin.me>

SVN-Revision: 49269

add support for Planex MZK-EX750NP.
MZK-EX750NP is MT7620A and MT7610E based 11ac wifi repeater.
Built-in power supply.
64MiB RAM, 8MiB SPI Flash, non Wired Ethernet.

Signed-off-by: YuheiOKAWA <tochiro.srchack@gmail.com>

SVN-Revision: 49268

Signed-off-by: John Crispin <blogic@openwrt.org>

SVN-Revision: 49265

Signed-off-by: Felix Fietkau <nbd@nbd.name>

So far fixtrx was calculating checksum over amount of data matching
partition erase size. It was mostly a workaround of checksum problem
after changing anything in initial TRX content (e.g. formatting JFFS2).
Its main purpose was to make bootloader accept modified TRX. This didn't
provide much protection of flash data against corruption.

This new option lets caller request calculating checksum over a bigger
amount of data. It may be used e.g. to include whole kernel data for
checksum and hopefully make bootloader go info failsafe mode if
something goes wrong.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>

We plan to adjust usage of the main buffer to allow reading custom
amount of data for CRC32. This means we need another buffer that will be
always block aligned.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>

1) Put sanity checks in one place
2) Respect provided offset
3) Read only as much data as needed for MD5 calculation

Thanks to the last change this is a great speedup and memory saver. On
devices with NAND flash we were allocating & reading about 128 MiB while
something about 8 MiB is enough.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>

This buf is only used in this function now, so lets move it there.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>

This will allow separating first block buffer from a buffer used for MD5
calculation.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>

This allows us to drop some extra offset calculations and simplifies
code a bit.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>

This avoid long (and unneeded) process of reading all data in case of
running on MTD not containig Seama entity.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>

On platforms supporting both: TRX and Seama calling "fixtrx" was
resulting in trying to fix Seama as well.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>

This makes code style consistent across the whole file.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>

Signed-off-by: Felix Fietkau <nbd@nbd.name>

Signed-off-by: Felix Fietkau <nbd@nbd.name>

Building for octeon fails with

  'arch/mips/vdso/vdso-o32.so.dbg' already contains a '.MIPS.abiflags'
  section

if the file already exists from a prior build.

Use the same workaround as the one for vdso.so.dbg committed in
9eb15535.

Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>

Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>

Fixes build with GCC 6.

Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>

Fixes the following error:

gdate.c: In function ‘g_date_strftime’:
gdate.c:2497:7: error: format not a string literal, format string not checked [-Werror=format-nonliteral]
       tmplen = strftime (tmpbuf, tmpbufsize, locale_format, &tm);
       ^~~~~~

Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>