ar71xx: ethernet: reduce tx and rx DMA ring size to improve cache footprint

256 entries is a bit excessive, even for gigabit speeds

Signed-off-by: Felix Fietkau <nbd@openwrt.org>

SVN-Revision: 37762

target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h

@@ -58,8 +58,8 @@
 #define AG71XX_TX_RING_SIZE_DEFAULT	64
 #define AG71XX_RX_RING_SIZE_DEFAULT	128
 
-#define AG71XX_TX_RING_SIZE_MAX		256
-#define AG71XX_RX_RING_SIZE_MAX		256
+#define AG71XX_TX_RING_SIZE_MAX		128
+#define AG71XX_RX_RING_SIZE_MAX		128
 
 #ifdef CONFIG_AG71XX_DEBUG
 #define DBG(fmt, args...)	pr_debug(fmt, ## args)