From e9b45ebaba6dbc17bfc0cd8085e53828216c1457 Mon Sep 17 00:00:00 2001
From: Gabor Juhos <juhosg@openwrt.org>
Date: Mon, 19 Mar 2012 11:11:20 +0000
Subject: [PATCH] ar71xx: add AR934x specific interface speed setup for ge0
SVN-Revision: 31017
---
.../linux/ar71xx/files/arch/mips/ath79/dev-eth.c | 13 +++++++++----
...01-MIPS-ath79-add-more-register-defines.patch | 16 ++++++++++++----
...01-MIPS-ath79-add-more-register-defines.patch | 16 ++++++++++++----
3 files changed, 33 insertions(+), 12 deletions(-)
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
index 2a55d33d82..d9880e0803 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
@@ -303,7 +303,12 @@ static void ar91xx_set_speed_ge1(int speed)
static void ar934x_set_speed_ge0(int speed)
{
- /* TODO */
+ void __iomem *base;
+ u32 val = ath79_get_eth_pll(0, speed);
+
+ base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
+ __raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG);
+ iounmap(base);
}
static void ath79_set_speed_dummy(int speed)
@@ -432,9 +437,9 @@ struct ag71xx_switch_platform_data ath79_switch_data;
#define AR933X_PLL_VAL_100 0x00001099
#define AR933X_PLL_VAL_10 0x00991099
-#define AR934X_PLL_VAL_1000 0x00110000
-#define AR934X_PLL_VAL_100 0x00001099
-#define AR934X_PLL_VAL_10 0x00991099
+#define AR934X_PLL_VAL_1000 0x16000000
+#define AR934X_PLL_VAL_100 0x00000101
+#define AR934X_PLL_VAL_10 0x00001616
static void __init ath79_init_eth_pll_data(unsigned int id)
{
diff --git a/target/linux/ar71xx/patches-3.2/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.2/601-MIPS-ath79-add-more-register-defines.patch
index 4d948bb29f..74b3c831f1 100644
--- a/target/linux/ar71xx/patches-3.2/601-MIPS-ath79-add-more-register-defines.patch
+++ b/target/linux/ar71xx/patches-3.2/601-MIPS-ath79-add-more-register-defines.patch
@@ -68,7 +68,15 @@
#define AR933X_PLL_CPU_CONFIG_REG 0x00
#define AR933X_PLL_CLOCK_CTRL_REG 0x08
-@@ -285,7 +305,11 @@
+@@ -165,6 +185,7 @@
+ #define AR934X_PLL_CPU_CONFIG_REG 0x00
+ #define AR934X_PLL_DDR_CONFIG_REG 0x04
+ #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
++#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c
+
+ #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
+ #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
+@@ -285,7 +306,11 @@
#define AR913X_RESET_USB_HOST BIT(5)
#define AR913X_RESET_USB_PHY BIT(4)
@@ -80,7 +88,7 @@
#define AR933X_RESET_USB_HOST BIT(5)
#define AR933X_RESET_USB_PHY BIT(4)
#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
-@@ -323,6 +347,8 @@
+@@ -323,6 +348,8 @@
#define AR934X_RESET_MBOX BIT(1)
#define AR934X_RESET_I2S BIT(0)
@@ -89,7 +97,7 @@
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
-@@ -427,6 +453,14 @@
+@@ -427,6 +454,14 @@
#define AR71XX_GPIO_REG_INT_ENABLE 0x24
#define AR71XX_GPIO_REG_FUNC 0x28
@@ -104,7 +112,7 @@
#define AR71XX_GPIO_COUNT 16
#define AR7240_GPIO_COUNT 18
#define AR7241_GPIO_COUNT 20
-@@ -434,4 +468,124 @@
+@@ -434,4 +469,124 @@
#define AR933X_GPIO_COUNT 30
#define AR934X_GPIO_COUNT 23
diff --git a/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch
index 4d948bb29f..74b3c831f1 100644
--- a/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch
+++ b/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch
@@ -68,7 +68,15 @@
#define AR933X_PLL_CPU_CONFIG_REG 0x00
#define AR933X_PLL_CLOCK_CTRL_REG 0x08
-@@ -285,7 +305,11 @@
+@@ -165,6 +185,7 @@
+ #define AR934X_PLL_CPU_CONFIG_REG 0x00
+ #define AR934X_PLL_DDR_CONFIG_REG 0x04
+ #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
++#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c
+
+ #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
+ #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
+@@ -285,7 +306,11 @@
#define AR913X_RESET_USB_HOST BIT(5)
#define AR913X_RESET_USB_PHY BIT(4)
@@ -80,7 +88,7 @@
#define AR933X_RESET_USB_HOST BIT(5)
#define AR933X_RESET_USB_PHY BIT(4)
#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
-@@ -323,6 +347,8 @@
+@@ -323,6 +348,8 @@
#define AR934X_RESET_MBOX BIT(1)
#define AR934X_RESET_I2S BIT(0)
@@ -89,7 +97,7 @@
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
-@@ -427,6 +453,14 @@
+@@ -427,6 +454,14 @@
#define AR71XX_GPIO_REG_INT_ENABLE 0x24
#define AR71XX_GPIO_REG_FUNC 0x28
@@ -104,7 +112,7 @@
#define AR71XX_GPIO_COUNT 16
#define AR7240_GPIO_COUNT 18
#define AR7241_GPIO_COUNT 20
-@@ -434,4 +468,124 @@
+@@ -434,4 +469,124 @@
#define AR933X_GPIO_COUNT 30
#define AR934X_GPIO_COUNT 23
--
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