From ca737049d22c3e630e715fc740b8f67cc6633150 Mon Sep 17 00:00:00 2001
From: John Crispin <john@openwrt.org>
Date: Mon, 25 Aug 2014 16:31:01 +0000
Subject: [PATCH] ralink: fix mt7620 ohci 3.10
the ohci phy was not reset properly
Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 42290
---
.../patches-3.10/0119-USB-phy-add-ralink-SoC-driver.patch | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/linux/ramips/patches-3.10/0119-USB-phy-add-ralink-SoC-driver.patch b/target/linux/ramips/patches-3.10/0119-USB-phy-add-ralink-SoC-driver.patch
index fbec32cacb..d71666e009 100644
--- a/target/linux/ramips/patches-3.10/0119-USB-phy-add-ralink-SoC-driver.patch
+++ b/target/linux/ramips/patches-3.10/0119-USB-phy-add-ralink-SoC-driver.patch
@@ -35,7 +35,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+obj-$(CONFIG_RALINK_USBPHY) += ralink-phy.o
--- /dev/null
+++ b/drivers/usb/phy/ralink-phy.c
-@@ -0,0 +1,191 @@
+@@ -0,0 +1,192 @@
+/*
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ *
@@ -66,6 +66,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+#define RT_SYSCFG1_USB0_HOST_MODE BIT(10)
+
+#define MT7620_CLKCFG1_UPHY0_CLK_EN BIT(25)
++#define MT7620_CLKCFG1_UPHY1_CLK_EN BIT(22)
+#define RT_CLKCFG1_UPHY1_CLK_EN BIT(20)
+#define RT_CLKCFG1_UPHY0_CLK_EN BIT(18)
+
@@ -145,7 +146,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+
+static const struct of_device_id ralink_usbphy_dt_match[] = {
+ { .compatible = "ralink,rt3xxx-usbphy", .data = (void *) (RT_CLKCFG1_UPHY1_CLK_EN | RT_CLKCFG1_UPHY0_CLK_EN) },
-+ { .compatible = "ralink,mt7620a-usbphy", .data = (void *) MT7620_CLKCFG1_UPHY0_CLK_EN },
++ { .compatible = "ralink,mt7620a-usbphy", .data = (void *) (MT7620_CLKCFG1_UPHY1_CLK_EN | MT7620_CLKCFG1_UPHY0_CLK_EN) },
+ {},
+};
+MODULE_DEVICE_TABLE(of, ralink_usbphy_dt_match);
--
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