diff --git a/target/linux/adm5120/files/arch/mips/adm5120/adm5120_info.c b/target/linux/adm5120/files/arch/mips/adm5120/adm5120_info.c
index 0abb961fd10e43a8e6ed2cfba024b8882973e33b..3e511064b3e3c708ebc0eb1d87ad0305c2b40aed 100644
--- a/target/linux/adm5120/files/arch/mips/adm5120/adm5120_info.c
+++ b/target/linux/adm5120/files/arch/mips/adm5120/adm5120_info.c
@@ -52,21 +52,21 @@ void adm5120_ndelay(u32 ns)
{
u32 t;
- SW_WRITE_REG(TIMER, TIMER_PERIOD_DEFAULT);
- SW_WRITE_REG(TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM));
+ SW_WRITE_REG(SWITCH_REG_TIMER, TIMER_PERIOD_DEFAULT);
+ SW_WRITE_REG(SWITCH_REG_TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM));
t = (ns+640) / 640;
t &= TIMER_PERIOD_MASK;
- SW_WRITE_REG(TIMER, t | TIMER_TE);
+ SW_WRITE_REG(SWITCH_REG_TIMER, t | TIMER_TE);
/* wait until the timer expires */
do {
- t = SW_READ_REG(TIMER_INT);
+ t = SW_READ_REG(SWITCH_REG_TIMER_INT);
} while ((t & TIMER_INT_TOS) == 0);
/* leave the timer disabled */
- SW_WRITE_REG(TIMER, TIMER_PERIOD_DEFAULT);
- SW_WRITE_REG(TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM));
+ SW_WRITE_REG(SWITCH_REG_TIMER, TIMER_PERIOD_DEFAULT);
+ SW_WRITE_REG(SWITCH_REG_TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM));
}
void __init adm5120_soc_init(void)
@@ -74,7 +74,7 @@ void __init adm5120_soc_init(void)
u32 code;
u32 clks;
- code = SW_READ_REG(CODE);
+ code = SW_READ_REG(SWITCH_REG_CODE);
adm5120_product_code = CODE_GET_PC(code);
adm5120_revision = CODE_GET_REV(code);
diff --git a/target/linux/adm5120/files/arch/mips/adm5120/gpio.c b/target/linux/adm5120/files/arch/mips/adm5120/gpio.c
index 01d5a87c4e50d9c00998dc97f7c9dbbb0b12b710..a7ae5497de08946578cee731e5178d64edfa6147 100644
--- a/target/linux/adm5120/files/arch/mips/adm5120/gpio.c
+++ b/target/linux/adm5120/files/arch/mips/adm5120/gpio.c
@@ -343,7 +343,7 @@ EXPORT_SYMBOL(adm5120_irq_to_gpio);
void __init adm5120_gpio_csx0_enable(void)
{
gpio_conf2 |= GPIO_CONF2_CSX0;
- SW_WRITE_REG(GPIO_CONF2, gpio_conf2);
+ SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2);
adm5120_gpio_map[ADM5120_GPIO_PIN1].flags &= ~GPIO_FLAG_VALID;
adm5120_gpio_map[ADM5120_GPIO_PIN2].irq = ADM5120_IRQ_GPIO2;
@@ -352,7 +352,7 @@ void __init adm5120_gpio_csx0_enable(void)
void __init adm5120_gpio_csx1_enable(void)
{
gpio_conf2 |= GPIO_CONF2_CSX1;
- SW_WRITE_REG(GPIO_CONF2, gpio_conf2);
+ SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2);
adm5120_gpio_map[ADM5120_GPIO_PIN3].flags &= ~GPIO_FLAG_VALID;
if (adm5120_package_bga())
@@ -362,7 +362,7 @@ void __init adm5120_gpio_csx1_enable(void)
void __init adm5120_gpio_ew_enable(void)
{
gpio_conf2 |= GPIO_CONF2_EW;
- SW_WRITE_REG(GPIO_CONF2, gpio_conf2);
+ SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2);
adm5120_gpio_map[ADM5120_GPIO_PIN0].flags &= ~GPIO_FLAG_VALID;
}
@@ -372,7 +372,7 @@ void __init adm5120_gpio_init(void)
int i;
gpio_conf2 = 0;
- SW_WRITE_REG(GPIO_CONF2, gpio_conf2);
+ SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2);
for (i = 0; i < ADM5120_GPIO_COUNT; i++)
adm5120_gpio_map[i].flags = GPIO_FLAG_VALID;
diff --git a/target/linux/adm5120/files/arch/mips/adm5120/memory.c b/target/linux/adm5120/files/arch/mips/adm5120/memory.c
index 79e9cb417a45f2061c6185a7338011bcc34a5a05..1803f2bfc592aba284950d8f56f4c6ea4c6519fd 100644
--- a/target/linux/adm5120/files/arch/mips/adm5120/memory.c
+++ b/target/linux/adm5120/files/arch/mips/adm5120/memory.c
@@ -82,7 +82,7 @@ static void __init adm5120_detect_memsize(void)
u32 size, maxsize;
u8 *p;
- memctrl = SW_READ_REG(MEMCTRL);
+ memctrl = SW_READ_REG(SWITCH_REG_MEMCTRL);
switch (memctrl & MEMCTRL_SDRS_MASK) {
case MEMCTRL_SDRS_4M:
maxsize = 4 << 20;
@@ -148,7 +148,7 @@ static void __init adm5120_detect_memsize(void)
memctrl |= MEMCTRL_SDRS_64M;
break;
}
- SW_WRITE_REG(MEMCTRL, memctrl);
+ SW_WRITE_REG(SWITCH_REG_MEMCTRL, memctrl);
}
out:
diff --git a/target/linux/adm5120/files/arch/mips/adm5120/reset.c b/target/linux/adm5120/files/arch/mips/adm5120/reset.c
index aa278fd2aa9e56e38319b6286428ca1f3abed0d9..bcdce5a109c5de9b92cd75c3deb0be2f97c48128 100644
--- a/target/linux/adm5120/files/arch/mips/adm5120/reset.c
+++ b/target/linux/adm5120/files/arch/mips/adm5120/reset.c
@@ -48,7 +48,7 @@ void adm5120_restart(char *command)
if (adm5120_board_reset)
adm5120_board_reset();
- SW_WRITE_REG(SOFT_RESET, 1);
+ SW_WRITE_REG(SWITCH_REG_SOFT_RESET, 1);
}
void adm5120_halt(void)
diff --git a/target/linux/adm5120/files/drivers/char/watchdog/adm5120_wdt.c b/target/linux/adm5120/files/drivers/char/watchdog/adm5120_wdt.c
index 982fe39c4960ffbda803152581657b7bf233b452..2439fbc7f21f3852ba14abb26d5cd6e7bb7aed97 100644
--- a/target/linux/adm5120/files/drivers/char/watchdog/adm5120_wdt.c
+++ b/target/linux/adm5120/files/drivers/char/watchdog/adm5120_wdt.c
@@ -1,5 +1,5 @@
/*
- * ADM5120_WDT 0.01: Infineon ADM5120 SoC watchdog driver
+ * ADM5120_WDT 0.01: Infineon ADM5120 SoC watchdog driver
* Copyright (c) Ondrej Zajicek <santiago@crfreenet.org>, 2007
*
* based on
@@ -47,26 +47,26 @@ MODULE_LICENSE("GPL");
static inline void wdt_set_timeout(void)
{
u32 val = (1 << 31) | (((timeout * 100) & 0x7FFF) << 16);
- SW_WRITE_REG(WDOG0, val);
+ SW_WRITE_REG(SWITCH_REG_WDOG0, val);
}
-/*
+/*
It looks like WDOG0-register-write don't modify counter,
but WDOG0-register-read resets counter.
*/
static inline void wdt_reset_counter(void)
{
- SW_READ_REG(WDOG0);
+ SW_READ_REG(SWITCH_REG_WDOG0);
}
static inline void wdt_disable(void)
{
- SW_WRITE_REG(WDOG0, 0x7FFF0000);
+ SW_WRITE_REG(SWITCH_REG_WDOG0, 0x7FFF0000);
}
-
+
static int wdt_open(struct inode *inode, struct file *file)
{
/* Allow only one person to hold it open */
diff --git a/target/linux/adm5120/files/drivers/mtd/maps/adm5120-flash.c b/target/linux/adm5120/files/drivers/mtd/maps/adm5120-flash.c
index 824d2f5e8e7fc41c2ea1a4fb70cde5d6c6db9235..b84492f46b239dfc4e5ffba7e753e4599fb0bd13 100644
--- a/target/linux/adm5120/files/drivers/mtd/maps/adm5120-flash.c
+++ b/target/linux/adm5120/files/drivers/mtd/maps/adm5120-flash.c
@@ -261,7 +261,7 @@ static int adm5120_flash_initinfo(struct adm5120_flash_info *info,
if (info->amap.window_size == 0) {
/* get memory window size */
- t = SW_READ_REG(MEMCTRL) >> fdesc->srs_shift;
+ t = SW_READ_REG(SWITCH_REG_MEMCTRL) >> fdesc->srs_shift;
t &= MEMCTRL_SRS_MASK;
info->amap.window_size = flash_sizes[t];
}
diff --git a/target/linux/adm5120/files/drivers/net/adm5120sw.c b/target/linux/adm5120/files/drivers/net/adm5120sw.c
index f876844060be427907c41fc1acf51c0ef7b01e59..c8c3f1d5b2aceca117e5855d8dd82be36ae83eeb 100644
--- a/target/linux/adm5120/files/drivers/net/adm5120sw.c
+++ b/target/linux/adm5120/files/drivers/net/adm5120sw.c
@@ -280,56 +280,56 @@ static void sw_dump_regs(void)
{
u32 t;
- t = SW_READ_REG(PHY_STATUS);
+ t = sw_read_reg(SWITCH_REG_PHY_STATUS);
SW_DBG("phy_status: %08X\n", t);
- t = SW_READ_REG(CPUP_CONF);
+ t = sw_read_reg(SWITCH_REG_CPUP_CONF);
SW_DBG("cpup_conf: %08X%s%s%s\n", t,
(t & CPUP_CONF_DCPUP) ? " DCPUP" : "",
(t & CPUP_CONF_CRCP) ? " CRCP" : "",
(t & CPUP_CONF_BTM) ? " BTM" : "");
- t = SW_READ_REG(PORT_CONF0);
+ t = sw_read_reg(SWITCH_REG_PORT_CONF0);
SW_DBG("port_conf0: %08X\n", t);
- t = SW_READ_REG(PORT_CONF1);
+ t = sw_read_reg(SWITCH_REG_PORT_CONF1);
SW_DBG("port_conf1: %08X\n", t);
- t = SW_READ_REG(PORT_CONF2);
+ t = sw_read_reg(SWITCH_REG_PORT_CONF2);
SW_DBG("port_conf2: %08X\n", t);
- t = SW_READ_REG(VLAN_G1);
+ t = sw_read_reg(SWITCH_REG_VLAN_G1);
SW_DBG("vlan g1: %08X\n", t);
- t = SW_READ_REG(VLAN_G2);
+ t = sw_read_reg(SWITCH_REG_VLAN_G2);
SW_DBG("vlan g2: %08X\n", t);
- t = SW_READ_REG(BW_CNTL0);
+ t = sw_read_reg(SWITCH_REG_BW_CNTL0);
SW_DBG("bw_cntl0: %08X\n", t);
- t = SW_READ_REG(BW_CNTL1);
+ t = sw_read_reg(SWITCH_REG_BW_CNTL1);
SW_DBG("bw_cntl1: %08X\n", t);
- t = SW_READ_REG(PHY_CNTL0);
+ t = sw_read_reg(SWITCH_REG_PHY_CNTL0);
SW_DBG("phy_cntl0: %08X\n", t);
- t = SW_READ_REG(PHY_CNTL1);
+ t = sw_read_reg(SWITCH_REG_PHY_CNTL1);
SW_DBG("phy_cntl1: %08X\n", t);
- t = SW_READ_REG(PHY_CNTL2);
+ t = sw_read_reg(SWITCH_REG_PHY_CNTL2);
SW_DBG("phy_cntl2: %08X\n", t);
- t = SW_READ_REG(PHY_CNTL3);
+ t = sw_read_reg(SWITCH_REG_PHY_CNTL3);
SW_DBG("phy_cntl3: %08X\n", t);
- t = SW_READ_REG(PHY_CNTL4);
+ t = sw_read_reg(SWITCH_REG_PHY_CNTL4);
SW_DBG("phy_cntl4: %08X\n", t);
- t = SW_READ_REG(INT_STATUS);
+ t = sw_read_reg(SWITCH_REG_INT_STATUS);
sw_dump_intr_mask("int_status: ", t);
- t = SW_READ_REG(INT_MASK);
+ t = sw_read_reg(SWITCH_REG_INT_MASK);
sw_dump_intr_mask("int_mask: ", t);
- t = SW_READ_REG(SHDA);
+ t = sw_read_reg(SWITCH_REG_SHDA);
SW_DBG("shda: %08X\n", t);
- t = SW_READ_REG(SLDA);
+ t = sw_read_reg(SWITCH_REG_SLDA);
SW_DBG("slda: %08X\n", t);
- t = SW_READ_REG(RHDA);
+ t = sw_read_reg(SWITCH_REG_RHDA);
SW_DBG("rhda: %08X\n", t);
- t = SW_READ_REG(RLDA);
+ t = sw_read_reg(SWITCH_REG_RLDA);
SW_DBG("rlda: %08X\n", t);
}
@@ -1061,7 +1061,7 @@ static int __init adm5120_switch_probe(struct platform_device *pdev)
(SWITCH_PORTS_PHY << PHY_CNTL2_PHYR_SHIFT) |
(SWITCH_PORTS_PHY << PHY_CNTL2_AMDIX_SHIFT) |
PHY_CNTL2_RMAE;
- SW_WRITE_REG(PHY_CNTL2, t);
+ sw_write_reg(SWITCH_REG_PHY_CNTL2, t);
t = sw_read_reg(SWITCH_REG_PHY_CNTL3);
t |= PHY_CNTL3_RNT;
diff --git a/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_nand.h b/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_nand.h
index 8d86fc6e78b328bd746206222db533285a10ee1b..a321db5d4a96d9fc84e89f41e7cec623b36ac5d1 100644
--- a/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_nand.h
+++ b/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_nand.h
@@ -65,8 +65,8 @@
static inline void adm5120_nand_enable(void)
{
- SW_WRITE_REG(BW_CNTL1, BW_CNTL1_NAND_ENABLE);
- SW_WRITE_REG(BOOT_DONE, 1);
+ SW_WRITE_REG(SWITCH_REG_BW_CNTL1, BW_CNTL1_NAND_ENABLE);
+ SW_WRITE_REG(SWITCH_REG_BOOT_DONE, 1);
}
static inline void adm5120_nand_set_wpn(unsigned int set)
diff --git a/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h b/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h
index f96c7d50c78c2ebb0eff4684cb5acf06120e8d00..9ed5233cb587c661513ad9df51c519b65c9c4e4e 100644
--- a/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h
+++ b/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h
@@ -32,9 +32,9 @@
#define BITMASK(len) ((1 << (len))-1)
#define SW_READ_REG(r) __raw_readl( \
- (void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + SWITCH_REG_ ## r)
+ (void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + r)
#define SW_WRITE_REG(r, v) __raw_writel((v), \
- (void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + SWITCH_REG_ ## r)
+ (void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + r)
/* Switch register offsets */
#define SWITCH_REG_CODE 0x0000