From b050f87d13b5dc7ed82feb9a90f4529de58bdf25 Mon Sep 17 00:00:00 2001 From: Felix Fietkau <nbd@openwrt.org> Date: Wed, 19 Feb 2014 19:20:10 +0000 Subject: [PATCH] gcc: prevent the use of LDRD/STRD on ARMv5TE These instructions are for 64-bit load/store. On ARMv5TE, the CPU requires addresses to be aligned to 64-bit. When misaligned, behavior is undefined (effectively either loads the same word twice on LDRD, or corrupts surrounding memory on STRD). On ARMv6 and newer, unaligned access is safe. Removing these instructions for ARMv5TE is necessary, because GCC ignores alignment information in pointers and does unsafe optimizations that have shown up as bugs in various places. Signed-off-by: Felix Fietkau <nbd@openwrt.org> SVN-Revision: 39638 --- .../4.6-linaro/800-arm_v5te_no_ldrd_strd.patch | 11 +++++++++++ .../4.8-linaro/800-arm_v5te_no_ldrd_strd.patch | 11 +++++++++++ .../gcc/patches/4.8.0/800-arm_v5te_no_ldrd_strd.patch | 11 +++++++++++ 3 files changed, 33 insertions(+) create mode 100644 toolchain/gcc/patches/4.6-linaro/800-arm_v5te_no_ldrd_strd.patch create mode 100644 toolchain/gcc/patches/4.8-linaro/800-arm_v5te_no_ldrd_strd.patch create mode 100644 toolchain/gcc/patches/4.8.0/800-arm_v5te_no_ldrd_strd.patch diff --git a/toolchain/gcc/patches/4.6-linaro/800-arm_v5te_no_ldrd_strd.patch b/toolchain/gcc/patches/4.6-linaro/800-arm_v5te_no_ldrd_strd.patch new file mode 100644 index 0000000000..4b7770d5d9 --- /dev/null +++ b/toolchain/gcc/patches/4.6-linaro/800-arm_v5te_no_ldrd_strd.patch @@ -0,0 +1,11 @@ +--- a/gcc/config/arm/arm.h ++++ b/gcc/config/arm/arm.h +@@ -232,7 +232,7 @@ extern void (*arm_lang_output_object_att + #define TARGET_BACKTRACE (leaf_function_p () \ + ? TARGET_TPCS_LEAF_FRAME \ + : TARGET_TPCS_FRAME) +-#define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN) ++#define TARGET_LDRD (arm_arch6 && ARM_DOUBLEWORD_ALIGN) + #define TARGET_AAPCS_BASED \ + (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS) + diff --git a/toolchain/gcc/patches/4.8-linaro/800-arm_v5te_no_ldrd_strd.patch b/toolchain/gcc/patches/4.8-linaro/800-arm_v5te_no_ldrd_strd.patch new file mode 100644 index 0000000000..ae4f6516ad --- /dev/null +++ b/toolchain/gcc/patches/4.8-linaro/800-arm_v5te_no_ldrd_strd.patch @@ -0,0 +1,11 @@ +--- a/gcc/config/arm/arm.h ++++ b/gcc/config/arm/arm.h +@@ -271,7 +271,7 @@ extern void (*arm_lang_output_object_att + /* Thumb-1 only. */ + #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) + +-#define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN \ ++#define TARGET_LDRD (arm_arch6 && ARM_DOUBLEWORD_ALIGN \ + && !TARGET_THUMB1) + + /* The following two macros concern the ability to execute coprocessor diff --git a/toolchain/gcc/patches/4.8.0/800-arm_v5te_no_ldrd_strd.patch b/toolchain/gcc/patches/4.8.0/800-arm_v5te_no_ldrd_strd.patch new file mode 100644 index 0000000000..ae4f6516ad --- /dev/null +++ b/toolchain/gcc/patches/4.8.0/800-arm_v5te_no_ldrd_strd.patch @@ -0,0 +1,11 @@ +--- a/gcc/config/arm/arm.h ++++ b/gcc/config/arm/arm.h +@@ -271,7 +271,7 @@ extern void (*arm_lang_output_object_att + /* Thumb-1 only. */ + #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) + +-#define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN \ ++#define TARGET_LDRD (arm_arch6 && ARM_DOUBLEWORD_ALIGN \ + && !TARGET_THUMB1) + + /* The following two macros concern the ability to execute coprocessor -- GitLab