From ac15780234f559c99eced96d1f9f725986c8fb64 Mon Sep 17 00:00:00 2001
From: Gabor Juhos <juhosg@openwrt.org>
Date: Mon, 10 Sep 2007 09:54:35 +0000
Subject: [PATCH] fix memory size detection (#2244)
SVN-Revision: 8728
---
target/linux/adm5120/files/arch/mips/adm5120/memory.c | 8 +++-----
.../files/include/asm-mips/mach-adm5120/adm5120_mpmc.h | 10 ++++++++--
2 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/target/linux/adm5120/files/arch/mips/adm5120/memory.c b/target/linux/adm5120/files/arch/mips/adm5120/memory.c
index 3881e9f6ab..605df26016 100644
--- a/target/linux/adm5120/files/arch/mips/adm5120/memory.c
+++ b/target/linux/adm5120/files/arch/mips/adm5120/memory.c
@@ -50,10 +50,11 @@ static int __init mem_check_pattern(u8 *addr, unsigned long offs)
u32 *p1 = (u32 *)addr;
u32 *p2 = (u32 *)(addr+offs);
u32 t,u,v;
+
/* save original value */
t = MEM_READL(p1);
- u = MEM_READL(p2);
+ u = MEM_READL(p2);
if (t != u)
return 0;
@@ -64,10 +65,7 @@ static int __init mem_check_pattern(u8 *addr, unsigned long offs)
mem_dbg("write 0x%08X to 0x%08lX\n", v, (unsigned long)p1);
MEM_WRITEL(p1, v);
-
- /* flush write buffers */
- MPMC_WRITE_REG(CTRL, MPMC_READ_REG(CTRL) | MPMC_CTRL_DWB);
-
+ adm5120_ndelay(1000);
u = MEM_READL(p2);
mem_dbg("pattern at 0x%08lX is 0x%08X\n", (unsigned long)p2, u);
diff --git a/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_mpmc.h b/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_mpmc.h
index 786f0f8c7e..406d6c563a 100644
--- a/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_mpmc.h
+++ b/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_mpmc.h
@@ -52,8 +52,14 @@
#define MPMC_REG_SC3 0x0260
/* Control register bits */
-#define MPMC_CTRL_AM ( 1 << 1 )
-#define MPMC_CTRL_DWB ( 1 << 3 )
+#define MPMC_CTRL_AM ( 1 << 1 ) /* Address Mirror */
+#define MPMC_CTRL_LPM ( 1 << 2 ) /* Low Power Mode */
+#define MPMC_CTRL_DWB ( 1 << 3 ) /* Drain Write Buffers */
+
+/* Status register bits */
+#define MPMC_STATUS_BUSY ( 1 << 0 ) /* Busy */
+#define MPMC_STATUS_WBS ( 1 << 1 ) /* Write Buffer Status */
+#define MPMC_STATUS_SRA ( 1 << 2 ) /* Self-Refresh Acknowledge*/
/* Dynamic Control register bits */
#define MPMC_DC_CE ( 1 << 0 )
--
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