From 6ebbb1329da150f18d048e856e8930738d5f3382 Mon Sep 17 00:00:00 2001
From: Gabor Juhos <juhosg@openwrt.org>
Date: Mon, 14 Nov 2011 17:43:14 +0000
Subject: [PATCH] ar71xx: add a function for selecting output signal on a given
GPIO pin
SVN-Revision: 29125
---
.../ar71xx/files/arch/mips/ar71xx/gpio.c | 31 +++++++++++++++++++
.../mips/include/asm/mach-ar71xx/ar71xx.h | 7 +++++
2 files changed, 38 insertions(+)
diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/gpio.c b/target/linux/ar71xx/files/arch/mips/ar71xx/gpio.c
index 2ab5dbcf1e..517a136a43 100644
--- a/target/linux/ar71xx/files/arch/mips/ar71xx/gpio.c
+++ b/target/linux/ar71xx/files/arch/mips/ar71xx/gpio.c
@@ -207,6 +207,37 @@ void ar71xx_gpio_function_setup(u32 set, u32 clear)
}
EXPORT_SYMBOL(ar71xx_gpio_function_setup);
+void __init ar71xx_gpio_output_select(unsigned gpio, u8 val)
+{
+ void __iomem *base = ar71xx_gpio_base;
+ unsigned long flags;
+ unsigned int reg;
+ u32 t, s;
+
+ if (ar71xx_soc != AR71XX_SOC_AR9341 &&
+ ar71xx_soc != AR71XX_SOC_AR9342 &&
+ ar71xx_soc != AR71XX_SOC_AR9344)
+ return;
+
+ if (gpio >= AR934X_GPIO_COUNT)
+ return;
+
+ reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4);
+ s = 8 * (gpio % 4);
+
+ spin_lock_irqsave(&ar71xx_gpio_lock, flags);
+
+ t = __raw_readl(base + reg);
+ t &= ~(0xff << s);
+ t |= val << s;
+ __raw_writel(t, base + reg);
+
+ /* flush write */
+ (void) __raw_readl(base + reg);
+
+ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
+}
+
void __init ar71xx_gpio_init(void)
{
int err;
diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
index 46057b3379..1f7f9eaf6c 100644
--- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
+++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
@@ -430,6 +430,12 @@ static inline u32 ar71xx_usb_ctrl_rr(unsigned reg)
#define AR71XX_GPIO_REG_INT_ENABLE 0x24
#define AR71XX_GPIO_REG_FUNC 0x28
+#define AR934X_GPIO_REG_OUT_FUNC0 0x2c
+#define AR934X_GPIO_REG_OUT_FUNC1 0x30
+#define AR934X_GPIO_REG_OUT_FUNC2 0x34
+#define AR934X_GPIO_REG_OUT_FUNC3 0x38
+#define AR934X_GPIO_REG_OUT_FUNC4 0x3c
+#define AR934X_GPIO_REG_OUT_FUNC5 0x40
#define AR934X_GPIO_REG_FUNC 0x6c
#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
@@ -499,6 +505,7 @@ void ar71xx_gpio_init(void) __init;
void ar71xx_gpio_function_enable(u32 mask);
void ar71xx_gpio_function_disable(u32 mask);
void ar71xx_gpio_function_setup(u32 set, u32 clear);
+void ar71xx_gpio_output_select(unsigned gpio, u8 val);
/*
* DDR_CTRL block
--
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