From 43422a634b743ed3d25a8631609a5293f187971b Mon Sep 17 00:00:00 2001 From: John Crispin <john@openwrt.org> Date: Thu, 17 Dec 2015 09:26:51 +0000 Subject: [PATCH] ramips: change CM_GCR_BASE_CMDEFTGT_MEM value to match datasheet Zero config value for default memory region means 'memory', not not 'disabled' according to 'Control Registers Of The Coherency Manager' manual. Signed-off-by: Nikolay Martynov <mar.kolya@gmail.com> SVN-Revision: 47906 --- ...CR_BASE_CMDEFTGT_MEM-according-to-datasheet.patch | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 target/linux/ramips/patches-4.3/0063-set-CM_GCR_BASE_CMDEFTGT_MEM-according-to-datasheet.patch diff --git a/target/linux/ramips/patches-4.3/0063-set-CM_GCR_BASE_CMDEFTGT_MEM-according-to-datasheet.patch b/target/linux/ramips/patches-4.3/0063-set-CM_GCR_BASE_CMDEFTGT_MEM-according-to-datasheet.patch new file mode 100644 index 0000000000..6b9e9e3bc0 --- /dev/null +++ b/target/linux/ramips/patches-4.3/0063-set-CM_GCR_BASE_CMDEFTGT_MEM-according-to-datasheet.patch @@ -0,0 +1,12 @@ +--- a/arch/mips/include/asm/mips-cm.h ++++ b/arch/mips/include/asm/mips-cm.h +@@ -225,8 +225,7 @@ BUILD_CM_Cx_R_(tcid_8_priority, 0x80) + #define CM_GCR_BASE_GCRBASE_MSK (_ULCAST_(0x1ffff) << 15) + #define CM_GCR_BASE_CMDEFTGT_SHF 0 + #define CM_GCR_BASE_CMDEFTGT_MSK (_ULCAST_(0x3) << 0) +-#define CM_GCR_BASE_CMDEFTGT_DISABLED 0 +-#define CM_GCR_BASE_CMDEFTGT_MEM 1 ++#define CM_GCR_BASE_CMDEFTGT_MEM 0 + #define CM_GCR_BASE_CMDEFTGT_IOCU0 2 + #define CM_GCR_BASE_CMDEFTGT_IOCU1 3 + -- GitLab