diff --git a/target/linux/ar71xx/patches-3.3/167-MIPS-ath79-add-USB-controller-registration-code-for-.patch b/target/linux/ar71xx/patches-3.3/167-MIPS-ath79-add-USB-controller-registration-code-for-.patch
index dd79296f60863b0ed5b132b17546f4c0c9f53244..5a27a9b714b666e4e0151f71c0168dbd25604142 100644
--- a/target/linux/ar71xx/patches-3.3/167-MIPS-ath79-add-USB-controller-registration-code-for-.patch
+++ b/target/linux/ar71xx/patches-3.3/167-MIPS-ath79-add-USB-controller-registration-code-for-.patch
@@ -86,7 +86,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  
 +#define QCA955X_EHCI0_BASE	0x1b000000
 +#define QCA955X_EHCI1_BASE	0x1b400000
-+#define QCA955X_EHCI_SIZE	0x1000
++#define QCA955X_EHCI_SIZE	0x200
 +
  /*
   * DDR_CTRL block
diff --git a/target/linux/ar71xx/patches-3.3/168-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch b/target/linux/ar71xx/patches-3.3/168-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch
index 5f88238267677b9a1e104ea7054f90b208b9b676..efc354e9d96fce51c2e44200b9a58a533628ef42 100644
--- a/target/linux/ar71xx/patches-3.3/168-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch
+++ b/target/linux/ar71xx/patches-3.3/168-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch
@@ -67,4 +67,4 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
 +#define QCA955X_WMAC_SIZE	0x20000
  #define QCA955X_EHCI0_BASE	0x1b000000
  #define QCA955X_EHCI1_BASE	0x1b400000
- #define QCA955X_EHCI_SIZE	0x1000
+ #define QCA955X_EHCI_SIZE	0x200
diff --git a/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch
index 84d7166ca1f4e8b8188746cd8b042eaf1a76dfeb..1d9ec4166a94171133856b6baab334ec61a34946 100644
--- a/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch
+++ b/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch
@@ -39,7 +39,7 @@
 @@ -112,6 +122,8 @@
  #define QCA955X_EHCI0_BASE	0x1b000000
  #define QCA955X_EHCI1_BASE	0x1b400000
- #define QCA955X_EHCI_SIZE	0x1000
+ #define QCA955X_EHCI_SIZE	0x200
 +#define QCA955X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
 +#define QCA955X_GMAC_SIZE	0x40